View ADP5053ACPZ-R7_8864801.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated power solu tion with quad buck regulators and supervisory circuits data sheet adp5053 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no respo nsibility is assu med by analo g d evic es fo r its u se, no r f or any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademark s and register ed trademark s are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 78 1.32 9.47 00 ? 2013 C 2016 analog devices, inc. all rights reserved. technica l support www.analog.com features wide input voltage range: 4.5 v to 15 .0 v 1.5% output accuracy over full temperature range 250 khz to 1.4 mhz adjustable switching frequency adjustable/fixed output options via factory fuse power regulation channel 1 and channel 2: programmable 1 .2 a/2.5 a/4 a sync buck regulators with low - side fet driver channel 3 and channel 4: 1.2 a sync buck regulators single 8 a output (channel 1 and channel 2 operated in parallel) precision enable with 0.8 v accurate threshold active output discharge switch fpwm or automatic pwm/psm selection frequency synchronization input or output optional latch - off protection on ovp /ocp failure power - good flag on selected channels uvlo, ocp, and tsd protection open - drain processor reset with external adjustable threshold monitoring watchdog refresh input manual reset input applications small cell base stations fpga and processor applications security and surveillance medical applications typical application circuit channel 2 buck regulator ( 1.2a/2.5a/4a ) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 l2 vreg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 l3 bst3 sw3 fb3 pgnd3 l4 vreg bst4 sw4 fb4 pgnd4 vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 c2 c1 c4 c3 c5 c6 c7 c8 c9 c10 c11 c12 c13 4.5v to 15v vout1 vout2 vout3 vout4 voutx r ilim1 r ilim2 vreg exposed pad ss12 c0 vdd watchdog and reset vth wdi mr rsto adp5053 channe l 1 buck regul a t or ( 1.2a/2.5a/4a ) channel 4 buck regulator (1.2a) pwrgd 1 1636-001 figure 1 . general descripti on the adp5053 combines four h igh performance buck regulators, a supervisory circuit , a watchdog timer , and a manual reset in a 48- lead lfcsp package that meets demanding performance and board s pace requirements. the device enables direct connection to high input voltages up to 15 .0 v with no preregulators. channel 1 and channel 2 integrate high - side power mosfet and low - side mosfet drivers. external nfets can be used in low - side power devices t o achieve an efficiency optimized solution and deliver a programmable output current of 1.2 a, 2.5 a, or 4 a. combining channel 1 and channel 2 in a parallel configuration can provide a single output with up to 8 a of current. channel 3 and channel 4 integ rate both high - side and low - side mosfets to deliver an output current of 1.2 a. the switching frequency of the adp5053 can be programmed or synchronized to an external clock. the adp5053 contains a precision enable pin on each channel for easy power - up sequencing or adjustable uvlo threshold. the adp5053 contains supervisory c ircuits that monitor the voltage level. the watchdog timer can generate a reset if the wdi pin is not toggle d within a preset timeout period. processor reset mode or system power on/off switch mode can be selected for manual reset functionality . table 1. family models model channels i 2 c package adp5050 four buck s , one ldo ye s 48 - lead lfcsp adp505 1 four buck s , s upervisory ye s 48 - lead lfcsp adp5052 four buck s , one ldo no 48 - lead lfcsp adp5053 four bucks, supervisory no 48 - lead lfcsp adp5054 four high current bucks no 48 - lead lfcsp
adp5053* product page quick links last content update: 11/04/2016 comparable parts view a parametric search of comparable parts evaluation kits ? adp5053 evaluation board documentation data sheet ? adp5053: integrated power solution with quad buck regulators and supervisory circuits data sheet tools and simulations ? adisimpower? voltage regulator design tool ? adp505x buck regulator design tool reference materials press ? tiny integrated solution powers rf agile radio applications and fpgas solutions bulletins & brochures ? integrated power solutions for altera fpgas ? integrated, high power solutions for xilinx fpgas design resources ? adp5053 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all adp5053 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
adp5053 data sheet rev. b | page 2 of 36 table of contents features .....................................................................................1 applications ...............................................................................1 typical application circuit ........................................................1 general description ..................................................................1 revision history ........................................................................2 detailed functional block diagram ..........................................3 specifications .............................................................................4 buck regulator specifications ................................................5 supervisory specifications .....................................................7 absolute maximum ratings ......................................................8 thermal re sistance ................................................................8 esd caution ..........................................................................8 pin configuration and function descriptions ...........................9 typical performance characteristics .......................................11 theory of operation ................................................................16 buck regula tor operational modes .....................................16 adjustable and fixed output voltages ................................. 16 internal regulators (vreg and vdd) ................................16 separate supply applications ...............................................17 low - side device selection ...................................................17 bootstrap circuitry ..............................................................17 active output discharge switch ..........................................17 precision enabling ...............................................................17 oscillator ..............................................................................17 synchronization input/output .............................................18 soft start ..............................................................................18 parallel operatio n ................................................................19 startup with precharged output ..........................................19 current - limit protection .....................................................19 frequency foldback .............................................................20 hiccup protection ................................................................20 latch - off protection ............................................................20 undervoltage lockout (uvlo) ...........................................21 power - good function .........................................................21 thermal shutdown .............................................................. 21 superviso ry circuit .............................................................. 21 applications information ........................................................ 23 adisimpower design tool .................................................. 23 programming the adjustable output voltage ...................... 23 voltage conversion limitations ........................................... 23 current - limit setti ng .......................................................... 23 soft start setting .................................................................. 24 inductor selection ............................................................... 24 output capacit or selection ................................................. 24 input capacitor selection .................................................... 25 low - side power device selection ........................................ 25 programming the uvlo input ........................................... 25 compensation components design .................................... 26 power dissipation ................................................................ 26 junction temperature .......................................................... 27 design example ....................................................................... 28 setting the switching frequency .......................................... 28 setting the output voltage ................................................... 28 setting the current limit ..................................................... 28 selecting the induc tor .......................................................... 28 selecting the output capacitor ............................................ 29 selecting the low - side mosfet ......................................... 29 designing the compensation network ................................ 29 selecting the soft start time ................................................ 29 selecting the input capacitor ............................................... 29 recommended external components ................................. 30 circuit board layout recommendations ................................ 31 ty p ical application circuits .................................................... 32 factory default options ...................................................... 35 outline dimensions ................................................................ 36 ordering guide ................................................................... 36 revision history 10/2016 rev. a to rev. b deleted factory programmable options section and table 16 to table 30; renumbered sequentially .........................................33 updated outline dimensions ..................................................34 9/ 2015 rev . 0 to r ev. a changes to table 1 ..................................................................... 1 11/ 2013 revision 0: initial version
data sheet adp5053 rev. b | page 3 of 36 detailed functional block diagram q1 q dg1 uvlo1 pvin1 sw1 bst1 vreg vreg driver driver pgnd dl1 control logic and mosfet driver with anticross protection control logic and mosfet driver with anticross protection en1 0.8v 1m? hiccup and latch-off ocp comp1 fb1 0.8v clk1 slope comp clk1 0.72v pwrgd1 zero cross current-limit selection frequency foldback + ? + ? + ? ? + + ? + ? + ? channel 1 buck regulator duplicate channel 1 channel 2 buck regulator current balance en2 comp2 fb2 dl2 pvin2 sw2 bst2 vid1 0.88v ovp latch-off ea1 cmp1 rt oscillator sync/mode soft start decoder ss12 ss34 vdd vreg internal regulator pvin1 vreg pwrgd house keeping logic uvlo3 pvin3 sw3 bst3 vreg vreg driver q3 q4 driver pgnd3 en3 comp3 fb3 channel 3 buck regulator duplicate channel 3 channel 4 buck regulator en4 comp4 fb4 pgnd4 pvin4 sw4 bst4 a cs1 + ? + ? a cs3 wdi reset generator 0.5v supervisory 0.8v 1m? hiccup and latch-off ocp 0.8v clk3 slope comp clk3 0.72v pwrgd3 frequency foldback + ? + ? + ? ? + + ? + ? vid3 0.88v ovp latch-off ea3 cmp3 zero cross vth debounce watchdog detector 1 1636-002 mr rsto figure 2 .
adp5053 data sheet rev. b | page 4 of 36 specifications v in = 12 v, v vreg = 5.1 v, t j = ?40c to +125c for minimum and maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 2. parameter symbol min ty p max unit test conditions/comments input supply voltage range v in 4.5 1 5.0 v pvin1, pvin2, pvin3, pvin4 pins quiescent current pvin1, pvin2, pvin3, pvin4 pins operating quiescent current i q 4.8 6. 3 5 ma no switching, all enx pins high i sh d n 25 65 a all enx pins low undervoltage lockout uvlo pvin1, pvin2, pvin3 , pvin4 pins threshold rising v u vlo - rising 4.2 4.36 v falling v u vlo - falling 3.6 3.78 v hysteresis v hys 0.42 v oscillator circuit switching frequency f sw 700 740 780 khz rt = 25.5 k? range 250 1400 khz sync input input clock range f syn c 250 1400 khz input clock pulse width minimum on time t sync_min_on 100 ns minimum off time t sync_min_off 100 ns input clock high voltage v h (syn c) 1.3 v inp ut clock low voltage v l (syn c) 0.4 v sync output clock frequency f clk f sw khz positive pulse duty cycle t clk_ pu lse_ du ty 50 % rise or fall time t clk_ rise_ fall 10 ns high level voltage v h (syn c_ ou t) v vreg v precision enabling en1, en2, en3, en4 pins high level threshold v th _ h (en ) 0.806 0.832 v low level threshold v th _ l (en ) 0.688 0.725 v pull - down resistor r pu ll - down (en ) 1.0 m? power good internal power - good rising threshold v pwrgd (ri se) 86.3 90.5 95 % hysteresis v pwrgd (h ys) 3.3 % falling delay t p w r g d _ fa l l 50 s rising delay for pwrgd pin t pwrgd_pin_rise 1 ms leakage current for pwrgd pin i pwrgd _ leakag e 0.1 1 a output low voltage for pwrgd pin v pwrg d_ low 50 100 mv i pwrgd = 1 ma internal regulators vdd output voltage v vdd 3.2 3.305 3.4 v i vdd = 10 ma current limit i lim_ vdd 20 51 80 ma vreg output voltage v vreg 4.9 5.1 5.3 v dropout voltage v dropout 225 mv i vreg = 50 ma current limit i li m _ vreg 50 95 140 ma thermal shutdown threshold t sh d n 150 c hysteresis t hys 15 c
data sheet adp5053 rev. b | page 5 of 36 buck regulator speci fications v in = 12 v, v vreg = 5.1 v, f sw = 600 khz for all cha nnels, t j = ?40c to +125c for minimum and maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 3. parameter symbol min ty p max unit test conditions/comments channel 1 sync buck regulato r fb1 pin fixed output options v ou t1 0.85 1.60 v fuse trim adjustable feedback voltage v fb1 0.800 v feedback voltage accuracy v fb1 ( d e fa u lt ) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb1 0.1 a adjustable voltage sw1 pin high - side power fet on resistance r d son (1h) 100 m? pin - to - pin measurement current - limit threshold i th (ilim1) 3.50 4.4 5.28 a r ilim1 = floating 1.91 2.63 3.08 a r ilim1 = 47 k? 4.95 6.44 7.48 a r ilim1 = 22 k? minimum on time t min_on1 117 155 ns f sw = 250 khz to 1.4 mhz minimum off time t m i n _ off1 1/9 t sw ns f sw = 250 khz to 1.4 mhz low - side driver, dl1 pin rising time t rising1 20 ns c i ss = 1.2 nf falling time t f alling 1 3.4 ns c i ss = 1.2 nf sourcing resistor t sou rci n g 1 10 ? sinking resistor t sinking1 0.95 ? error amplifier (ea), comp1 pin ea transconductance g m1 310 470 620 s soft start soft start time t ss1 2.0 ms ss12 connected to vr eg programmable soft start range 2.0 8.0 ms hiccup time t hiccup1 7 t ss1 ms c out discharge switch on resistance r d i s1 250 ? channel 2 sync buck regulator fb2 pin fixed output options v ou t2 3.3 5.0 v fuse trim adjustable feedba ck voltage v fb2 0.800 v feedback voltage accuracy v fb2 ( d e fa u lt ) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb2 0.1 a adjustable voltage sw2 pin high - side power fet o n resistance r d son (2h) 110 m? pin - to - pin measurement current - limit threshold i th (ilim2) 3.50 4.4 5.28 a r ilim2 = floating 1.91 2.63 3.08 a r ilim2 = 47 k? 4.95 6.44 7.48 a r ilim2 = 22 k? minimum on time t min_on2 117 155 ns f sw = 250 khz to 1.4 mhz minimum off time t m i n _ off2 1/9 t sw ns f sw = 250 khz to 1.4 mhz low - side driver, dl2 pin rising time t rising2 20 ns c i ss = 1.2 nf falling time t falling 2 3.4 ns c i ss = 1.2 nf sourcing resistor t sou rci n g 2 10 ? sinking resistor t si n k ing2 0.95 ?
adp5053 data sheet rev. b | page 6 of 36 parameter symbol min ty p max unit test conditions/comments error amplifier (ea), comp2 pin ea transconductance g m2 310 470 620 s soft start soft start time t ss2 2.0 ms ss12 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup2 7 t ss2 ms c out d ischarge switch on resistance r d i s2 250 ? channel 3 sync buck regulator fb3 pin fixed output options v ou t3 1.20 1.80 v fuse trim adjustable feedback voltage v fb3 0.800 v feedback voltage accuracy v fb3 ( d e fa u lt ) ?0.55 +0.55 % t j = 2 5c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb3 0.1 a adjustable voltage sw3 pin high - side power fet on resistance r d son (3h) 225 m? pin - to - pin measurement low - side power fet on resistance r d son (3 l) 150 m? pin - to - pin measurement current - limit threshold i th (ilim3) 1.7 2.2 2.55 a minimum on time t min_on3 90 120 ns f sw = 250 khz to 1.4 mhz minimum off time t m i n _ off3 1/9 t sw ns f sw = 250 khz to 1.4 mhz error amplifier (ea), comp3 p in ea transconductance g m3 310 470 620 s soft start soft start time t ss3 2.0 ms ss34 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup3 7 t ss3 ms c out discharge switch on resistance r d i s3 250 ? channel 4 sync buck regulator fb4 pin fixed output options v ou t4 2.5 5.5 v fuse trim adjustable feedback voltage v fb4 0.800 v feedback voltage accuracy v fb4 ( d e fa u lt ) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 + 1.5 % ?40c t j +125c feedback bias current i fb4 0.1 a adjustable voltage sw4 pin high - side power fet on resistance r d son (4h) 225 m? pin - to - pin measurement low - side power fet on resistance r d son (4 l) 150 m? pin - to - pin measurement cu rrent - limit threshold i th (ilim4) 1.7 2.2 2.55 a minimum on time t min_on4 90 120 ns f sw = 250 khz to 1.4 mhz minimum off time t m i n _ off4 1/9 t sw ns f sw = 250 khz to 1.4 mhz error amplifier (ea), comp4 pin ea transconductance g m4 310 470 620 s soft start soft start time t ss4 2.0 ms ss34 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup4 7 t ss4 ms c out discharge switch on resistance r d i s4 250 ?
data sheet adp5053 rev. b | page 7 of 36 supervisory specific ations v in = 12 v, v vreg = 5.1 v , t j = ?40c to +125c for minimum and maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 4. parameter symbol min ty p max unit t est conditions/comments threshold voltage v th 0.494 0.500 0.505 v reset timeout period t rp option 0 1.05 1.4 1.97 ms option 1 21 28 38 ms option 2 160 200 260 ms option 3 1.15 1.6 2.17 sec v cc to reset delay t rd 80 s vth falling a t 1 mv/ s watchdog input watchdog timeout period t wd option 0 4.8 6.3 8 ms option 1 79 102 135 ms option 2 1.14 1.6 2.15 sec option 3 25.6 sec wdi pulse width 80 ns wdi input threshold 0.4 1.2 v wdi input current (sou rce) 8.5 14 18.5 a v wdi = v cc , time average wdi input current (sink) ?15 ?22 ?30 a v wdi = 0 v, time average manual reset input mr input pulse width 1 s mr glitch rejection 280 ns mr pull - up resistance 32 55 80 k? mr to reset delay 310 ns
adp5053 data sheet rev. b | page 8 of 36 absolute maximum rat ings table 5. parameter rating pvin1 to pgnd ?0.3 v to +18 v pvin2 to pgnd ?0.3 v to +18 v pvin3 to pgnd3 ?0.3 v to +1 8 v pvin4 to pgnd4 ?0.3 v to +18 v sw1 to pgnd ?0.3 v to +18 v sw2 to pgnd ?0.3 v to +18 v sw3 to pgnd3 ?0.3 v to +18 v sw4 to pgnd4 ?0.3 v to +18 v pgnd to gnd ?0.3 v to +0.3 v pgnd3 to gnd ?0.3 v to +0.3 v pgnd4 to gnd ?0.3 v to +0.3 v bst1 to s w1 ?0.3 v to +6.5 v bst2 to sw2 ?0.3 v to +6.5 v bst3 to sw3 ?0.3 v to +6.5 v bst4 to sw4 ?0.3 v to +6.5 v dl1 to pgnd ?0.3 v to +6.5 v dl2 to pgnd ?0.3 v to +6.5 v ss12, ss34 to gnd ?0.3 v to +6.5 v en1, en2, en3, en4 to gnd ?0.3 v to +6.5 v vreg to gnd ?0.3 v to +6.5 v sync/mode to gnd ?0.3 v to +6.5 v wdi, rsto , vth to gnd ?0.3 v to +6.5 v mr to gnd ?0.3 v to +3.6 v rt to gnd ?0.3 v to +3.6 v pwrgd to gnd ?0.3 v to +6.5 v fb1, fb2, fb3, fb4 to gnd 1 ?0.3 v to +3.6 v fb2 to gnd 2 ?0.3 v to +6.5 v fb4 to gnd 2 ?0.3 v to +7 v comp1, comp2, comp3, comp4 to gnd ?0.3 v to +3.6 v vdd to gnd ?0.3 v to +3.6 v storage temperate range ?65c to +150c operational junction temperature range ?40c to +125c 1 this rating applies to the adjustable output voltage models of the adp5053 . 2 this rating applies to the fixed output voltage models of the adp5053 . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operatio nal section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circ uit board for surface - mount packages. table 6 . thermal resistance package type ja jc unit 48 - lead lfcsp 27.87 2.99 c/w esd caution
data sheet adp5053 rev. b | page 9 of 36 pin configuration an d function descripti ons 1 2 3 pvin1 pvin1 sw1 4 sw1 5 bst1 6 dl1 7 pgnd 24 pvin2 23 en2 22 comp2 21 fb2 20 pwrgd 19 gnd 18 gnd 17 gnd 16 fb4 15 comp4 14 en4 13 gnd 44 vreg 45 fb3 46 comp3 47 ss34 48 en3 43 sync/mode 42 vdd 41 rt 40 fb1 39 comp1 38 ss12 37 en1 top view (not to scale) adp5053 25 bst4 26 pgnd4 27 sw4 28 pvin4 29 30 31 vth 32 wdi 33 pvin3 34 sw3 35 pgnd3 36 bst3 notes 1. the exposed pad must be connected and soldered to an external ground plane. 8 dl2 9 bst2 10 sw2 11 sw2 12 pvin2 11636-003 mr rsto figure 3 . pin c onfiguration table 7 . pin function descriptions pin no. mnemonic description 1 bst3 high - side fet driver power supply for channel 3. 2 pgnd3 power ground for channel 3. 3 sw3 switching node output for channel 3. 4 pvin3 power input for channel 3. connect a bypass capacitor between this pin and ground. 5 wdi watchdog refresh input from p rocessor. 6 vth monitoring voltage threshold programming . 7 mr manual reset input , active low . 8 rsto o pen - drain reset output, active low. 9 pvin4 power input for channel 4. connect a bypass capacitor between this pin and ground. 10 sw4 switching node output for channel 4. 11 pgnd4 power ground for channel 4. 12 bst4 high - side fet driver power supply f or channel 4. 13 gnd this pin is for internal test purposes. connect this pin to ground. 14 en4 enable input for channel 4. use a n external resistor divider to set the turn - on threshold. 15 comp4 error amplifier output for channel 4. connect an rc netwo rk from this pin to ground. 16 fb4 feedback sensing input for channel 4. 17, 18, 19 gnd these pins are for internal test purposes. connect these pins to ground. 20 pwrgd power - good signal output. this open - drain output is the power - good signal for the selected channels. 21 fb2 feedback sensing input for channel 2. 22 comp2 error amplifier output for channel 2. connect an rc network from this pin to ground. 23 en2 enable input for channel 2. use a n external resistor divider to set the turn - on threshol d. 24, 25 pvin2 power input for channel 2. connect a bypass capacitor between this pin and ground. 26, 27 sw2 switching node output for channel 2. 28 bst2 high - side fet driver power supply for channel 2. 29 dl2 low - side fet gate driver for channel 2. c onnect a resistor from this pin to ground to program the current - limit threshold for channel 2. 30 pgnd power ground for channel 1 and channel 2. 31 dl1 low - side fet gate driver for channel 1. connect a resistor from this pin to ground to program the cur rent - limit threshold for channel 1.
adp5053 data sheet rev. b | page 10 of 36 pin no. mnemonic description 32 bst1 high - side fet driver power supply for channel 1. 33, 34 sw1 switching node output for channel 1. 35, 36 pvin1 power input for the internal 5.1 v vreg linear regulator and the channel 1 buck regulator. connect a bypass capacitor between this pin and ground. 37 en1 enable input for channel 1. an external resistor divider can be used to set the turn - on threshold. 38 ss12 connect a resistor divider from this pin to vreg and ground to configure the soft start time for channel 1 and channel 2 (see the soft start section). this pin is also used to configure parallel operation of channel 1 and channel 2 (see the parallel operation section). 39 comp1 error amplifier output for channel 1. connect an rc network from this pin to ground. 40 fb1 feedback sensing input for channel 1. 41 rt frequency setting. connect a resistor from rt to ground to program the switching frequency from 250 khz to 1.4 mhz. fo r more information, see the oscillator section. 42 vdd output of the internal 3.3 v linear regulator. connect a 1 f ceramic capacitor between this pin and ground. 43 sync/mode synchronization input/output (sync) . to synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 250 khz to 1.4 mhz. th e sync function of this pin can also be configured as a synchronization output by factory fuse. forced pwm or automatic pwm/psm selection pin (mode). when this pin is logic high, the device operates in forced pwm (fpwm) mode. when this pin is logic low, the device operates in automatic pwm/psm mode. 44 vreg output of the internal 5.1 v linear regu lator. connect a 1 f ceramic capacitor between this pin and ground. 45 fb3 feedback sensing input for channel 3. 46 comp3 error amplifier output for channel 3. connect an rc network from this pin to ground. 47 ss34 connect a resistor divider from this pin to vreg and ground to configure the soft start time for channel 3 and channel 4 (see the soft start section). 48 en3 enable input for channel 3. use a n external resistor divider to set the turn - on threshold. 0 epa d exposed pad (analog ground). the exposed pad must be connected and soldered to an external ground plane.
data sheet adp5053 rev. b | page 11 of 36 typical performance characteristics 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) v out = 1 . 2 v v out = 1 . 5 v v out = 1 . 8 v v out = 2 . 5 v v out = 3 . 3 v v out = 5 . 0 v 1 1636-103 figure 4 . channel 1/channel 2 efficiency curve, v in = 12 v, f sw = 600 khz, f pwm mode 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) v out = 1 . 2 v v out = 1 . 5 v v out = 1 . 8 v v out = 2 . 5 v v out = 3 . 3 v 1 1636-004 figure 5 . channel 1/channel 2 efficiency curve, v in = 5.0 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) f sw = 1.0mhz f sw = 600khz f sw = 300khz 1 1636-005 figure 6 . channel 1/channel 2 efficiency curve, v in = 12 v, v out = 1.8 v, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficienc y (%) i out (a) v out = 1 . 2 v , fpwm v out = 1 . 2 v , au t o pwm/psm v out = 1 . 8v , fpwm v out = 1 . 8v , au t o pwm/psm v out = 3.3 v , fpwm v out = 3.3 v , au t o pwm/psm 1 1636-006 figure 7 . channel 1/channel 2 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm and automatic pwm/psm modes 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) v out = 1 . 2 v v out = 1 . 5 v v out = 1 . 8 v v out = 2 . 5 v v out = 3 . 3 v v out = 5 . 0 v 1 1636-007 figure 8 . channel 3/channel 4 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) v out = 1 . 2 v v out = 1 . 5 v v out = 1 . 8 v v out = 2 . 5 v v out = 3 . 3 v 1 1636-008 figure 9 . channel 3/channel 4 efficiency curve, v in = 5.0 v, f sw = 600 khz, fpwm mode
adp5053 data sheet rev. b | page 12 of 36 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) f sw = 1.0mhz f sw = 600khz f sw = 300khz 1 1636-009 figure 10 . channel 3/channel 4 efficiency curve, v in = 12 v, v out = 1.8 v, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 2 efficienc y (%) i out (a) v out = 1 . 2 v , fpwm v out = 1 . 2 v , au t o pwm/psm v out = 1 . 8v , fpwm v out = 1 . 8v , au t o pwm/psm v out = 3.3 v , fpwm v out = 3.3 v , au t o pwm/psm 1 1636-010 figure 11 . channel 3/c hannel 4 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm and automatic pwm/psm modes ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 1 2 3 4 load regul a tion (%) i out (a) 1 1636-0 1 1 figure 12 . channel 1 load regulation, v in = 12 v, v out = 3.3 v, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 line regul a tion (%) input vo lt age (v) 1 1636-012 figure 13 . channel 1 l ine regulation, v out = 3.3 v, i out = 4 a, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 load regul a tion (%) i out (a) 1 1636-013 figure 14 . channel 3 load regulation, v in = 12 v, v out = 3.3 v, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 line regul a tion (%) input vo lt age (v) 1 1636-014 figure 15 . channel 3 line regulation, v ou t = 3.3 v, i out = 1 a, f sw = 600 khz, fpwm mode
data sheet adp5053 rev. b | page 13 of 36 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?50 ?20 10 40 70 100 130 feedback vol t age accurac y (%) temperature (c) 11636-015 figure 16. 0.8 v feedback voltage accuracy vs. temperature for channel 1, adjustable output model 550 600 650 700 750 800 850 ?50 ?20 10 40 70 100 130 frequency (khz) temperature (c) 11636-017 figure 17. frequency vs. temperature, v in = 12 v 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?50 0 25 ?25 50 75 125 100 150 quiescent current (ma) temperature (c) 11636-018 figure 18. quiescent current vs. temperature (includes pvin1, pvin2, pvin3, and pvin4) 15 25 35 45 55 65 75 shutdown current (a) temperature (c) ?50 0 25 ?25 50 75 125 100 150 v in = 4.5v v in = 7.0v v in = 12v v in = 15v 11636-019 figure 19. shutdown current vs. temperature (en1, en2, en3, and en4 low) 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 ?50 ?20 10 40 70 100 130 uvlo threshold (v) temperature (c) rising falling 11636-020 figure 20. uvlo threshold vs. temperature 0 1 2 3 4 5 6 7 4 6 8 10121416 current limit (a) input voltage (v) r ilim =22k ? r ilim =open r ilim = 47k ? 11636-021 figure 21. channel 1/channel 2 current limit vs. input voltage
adp5053 data sheet rev. b | page 14 of 36 0 20 40 60 80 100 120 140 160 180 200 ?50 ?20 10 40 70 100 130 minimum on time (ns) temper a ture (c) c h anne l 1 / c h anne l 2 c h anne l 3 / c h anne l 4 1 1636-022 figure 22 . minimum on time vs. temperature ch1 5.00v ch2 10.0m v b w m1.00s a ch1 7.40v 2 1 v out swx 1 1636-028 figure 23 . steady state wave form at heavy load, v in = 12 v, v out = 3.3 v, i out = 3 a, f sw = 600 khz, l = 4.7 h, c out = 47 f 2, fpwm mode ch1 5.00v ch2 50.0m v b w m100s a ch1 11.0mv 2 1 v out swx 1 1636-029 figure 24 . steady state waveform at light load, v in = 12 v, v out = 3.3 v, i out = 30 ma, f sw = 600 khz, l = 4.7 h, c out = 47 f 2, automatic pwm/psm mode ch1 50.0m v b w ch4 2.00a ? m100s a ch1 ?22.0mv 1 4 v out i out 1 1636-030 figure 25 . channel 1/channel 2 load transient, 1 a to 4 a, v in = 12 v, v out = 3.3 v, f sw = 600 khz, l = 2.2 h, c out = 47 f 2 ch3 2.00a ? b w ch4 2.00a ? b w ch2 100mv b w m100s a ch2 ?56.0mv 2 4 v out i out2 i out1 1 1636-031 figure 26 . load transi ent, channel 1/channel 2 parallel output, 0 a to 6 a, v in = 12 v, v out = 3.3 v, f sw = 600 khz, l = 4.7 h, c out = 47 f 4 ch1 500m v b w ch2 5.00v ch3 5.00 v b w ch4 2.00a ? m1.00ms a ch1 650mv 1 3 2 4 v out i out en1/en2 pwrgd 1 1636-032 figure 27 . channel 1/channel 2 soft start with 4 a resistance load, v in = 12 v, v out = 1.2 v, f sw = 60 0 khz, l = 1 h, c out = 47 f 2
data sheet adp5053 rev. b | page 15 of 36 ch3 1.00v b w ch1 10.0v b w ch4 1.00a ? b w ch2 5.00v b w m400s a ch2 2.80v 1 4 2 3 v in v out en1/en2 i out 1 1636-033 figure 28 . startup with precharged output, v in = 12 v, v out = 3.3 v ch3 5.00v b w ch1 500mv b w ch4 5.00a ? b w ch2 5.00v b w m10.0ms a ch1 650mv 1 4 2 3 v out i out en1/en2 pwrgd 1 1636-034 figure 29 . channel 1/channel 2 shutdown with active output discharge, v in = 12 v, v out = 1.2 v , f sw = 600 khz, l = 1 h, c out = 47 f 2 1 1636-135 ch1 500mv b w ch4 5.00a ? ch2 10.00v b w m10.0ms a ch1 970mv 1 4 2 v out i out swx figure 30 . short - circuit protection entry, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 1 1636-136 ch1 500mv b w ch4 5.00a ? b w ch2 10.0v b w m10.0ms a ch1 970mv 1 4 2 v out i out swx figure 31 . short - circuit protection recov ery, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2
adp5053 data sheet rev. b | page 16 of 36 theory of operation the adp5053 is a micropower management unit that combines four high performance buck regulators in a 48 - lead lfcsp package to meet demanding performance and board space requirements. the device enables direct connection to high input voltages up to 15 .0 v with no preregulators to make applications simpler and more efficient. buck regulator opera tiona l modes pulse - width modulation (pwm) mode in pwm mode, the buck regulators in the adp5053 operate at a fixed frequency; this frequency is set by an internal oscillator that is programmed by the r t pin . at the start of each oscillator cycle, the high - side mosfet turns on and sends a positive voltage across the inductor. the inductor current increases until the current sense signal exceeds the peak inductor current threshold that turns off the high - side mosfet; this threshold is set by the error amplifier output. during the high - side mosfet off time, the inductor current decreases through the low - side mosfet until the next oscillator clock pulse starts a new cycle. the buck regulators in the adp5053 regulate the output voltage by adjusting the peak inductor current threshold. power save mode (psm) to achieve higher efficiency, the buck regulators in the adp5053 smoothly transition to variable frequency psm operation when the output load falls below the psm current threshold. when the output voltage falls below regulation, the buck regulator enters pwm mode for a few oscillator cycl es until the voltage increases to within regulation. during the idle time between bursts, the mosfet turns off, and the output capacitor supplies all the output current. the psm comparator monitors the internal compensation node, which represents the peak inductor current information. the average psm current threshold depends on the input voltage (v in ), the output voltage (v out ), the inductor, and the output capacitor. because the output voltage occasionally falls below regulation and then recovers, the out put voltage ripple in psm operation is larger than the ripple in the forced pwm mode of operation under light load conditions. forced pwm and automatic pwm/psm modes the buck regulators can be configured to always operate in pwm mode using the sync/mode pi n. in forced pwm (fpwm) mode, the regulator continues to operate at a fixed frequency even when the output current is below the pwm/psm threshold. in pwm mode, efficiency is lower when compared to psm mode under light load conditions. the low - side mosfet r emains on when the inductor current falls to less than 0 a, causing the adp5053 to enter continuous conduction mode (ccm). the buck regulators can be configured to operate in automatic pwm/psm mode using the sync/mode pin. in automatic pwm/psm mode, the buck regulators operate in either pwm mode or psm mode, depending on the output current. when the average output current falls below the pwm/psm threshold, the buck regulator enters psm mode oper ation; in psm mode, the regulator operates with a reduced switching frequency to maintain high efficiency. the low - side mosfet turns off when the output current reaches 0 a, causing the regulator to operate in discontinuous mode (dcm). when the sync/mode p in is connected to vreg, the device operates in forced pwm (fpwm) mode. when the sync/ mode pin is connected to ground, the device operates in automatic pwm/psm mode . adjustable and fixed output voltages the adp5053 provides adjustable and fixed output voltage settings via factory fuse. for the adjustable output settings, use an external resistor divider to set the desired output voltage via the feedback reference voltage (0.8 v for channel 1 to c hannel 4). for the fixed output settings, the feedback resistor divider is built into the adp5053 , and the feedback pin (fbx) must be tied directly to the output. table 8 lists the available fixed output voltage ranges for each buck regulator channel. table 8 . fixed output voltage ranges channel fixed output voltage range channel 1 0.85 v to 1.6 v in 25 mv steps channel 2 3.3 v to 5.0 v in 300 mv or 200 mv steps channel 3 1.2 v to 1.8 v in 100 mv steps channel 4 2.5 v to 5.5 v in 100 mv steps the output range can also be programmed by factory fuse. if a different output voltage range is required, contact your local analog devices, i nc., sales or distribution representative. internal regulators (vreg and vdd) the internal vreg regulator in the adp5053 provides a stable 5.1 v power supply for the bias voltage of the mosfet dr ivers. the internal vdd regulator in the adp5053 provides a stable 3.3 v power supply for internal control circuits. connect a 1.0 f ceramic capacitor between vreg and ground; connect another 1. 0 f ceramic capacitor between vdd and ground. the internal vreg and vdd regulators are active as long as pvin1 is available. the internal vreg regulator can provide a total load of 95 ma including the mosfet driving current, and it can be used as an alwa ys alive 5.1 v power supply for a small system current demand. the current - limit circuit is included in the vreg regulator to protect the circuit when the dev ice is heavily loaded . the vdd regulator is strictly for internal circuit use and is not recommend ed for other purposes.
data sheet adp5053 rev. b | page 17 of 36 separate supply appl ications the adp5053 supports separate input voltages for the four buck regulators. this means that the input voltages for the four buck regulators can be connected to different supply voltages. the pvin1 voltage provides the power supply for the internal regulators and the control circuitry. therefore, if the user plans to use separate supply voltages for the buck regulators, the pvin1 voltage must be ab ove the uvlo threshold before the other channels begin to operate. t o ensure that pvin1 is high enough to support the outputs in regulation , use p recision enabling to monitor the pvin1 voltage and to delay the startup of the outputs. for more information, see the precision enabling section. the adp5053 supports cascading supply operation for the four buck regulators. as shown in figure 32 , pvin2, pvin3, and pvin4 are powered from the channel 1 output (v out1 ) . in this configuration, the channel 1 output voltage must be higher than the uvlo threshold for pvin2, pvin3, and pvin4. pvin1 buck 1 buck 2 v out1 pvin2 to pvin4 v out2 to v out4 v in 1 1636-037 figure 32 . cas cading supply application low - side device selectio n the buck regulators in channel 1 and channel 2 integrate 4 a high - side power mosfet and low - side mosfet drivers. the n - channel mosfets selected for use with the adp5053 must be compatible with the synchronized buck regulators. in general, a low r dson n - channel mosfet achieve s higher efficiency; dual mosfets in one package (for both channel 1 and channel 2) are recommended to save space on the pri nted circuit board ( pcb ) . for more information, see the low - side power device selection section. bootstrap circuitry each buck regulator in the adp5053 h as an integrated bootstrap regulator. the bootstrap regulator requires a 0.1 f ceramic capacitor (x5r or x7r) between the bstx and swx pins to provide the gate drive voltage for the high - side mosfet. active output discha rge switch each buck regulator in t he adp5053 integrates a discharge switch from the switching node to ground. this switch is turned on when its associated regulator is disabled, which helps to discharge the output capacitor quick ly. the typical value of the discharge switch is 250 ? for channel 1 to channel 4. enable or disable t he discharge switch function for all four buck regulators by factory fuse. precision enabling the adp5053 has an enable con trol pin for each regulator . the enable control pin (enx) features a precision enable circuit with a 0.8 v reference voltage. a voltage greater than 0.8 v at the enx pin enables the regulator. a voltage less than 0.725 v at t he enx pin disables the regulator. an internal 1 m? pull - down resistor prevents errors when the enx pin is left floating. the precision enable threshold voltage allows easy sequencing of channels within the device , as well as sequencing between the adp5053 and other input/output supplies. the enx pin can also be used as a programmable uvlo input using a resistor divider (see figure 33 ). for more information, see the programming the u vlo input section. 0.8v deglitch timer interna l enable enx r1 r2 1m? input/output vo lt age adp5053 1 1636-038 figure 33 . precision enable diagram for one channel oscillator the switching frequency (f sw ) of the adp5053 can be set to a value from 250 khz to 1. 4 mhz by connecting a resistor from the rt pin to ground. calculate t he value of the rt resistor as follows: r rt (k?) = [14,822/ f sw (khz)] 1. 081 figure 34 shows the typical relationship between the switching frequency ( f sw ) and the rt resistor. the adjustable frequency allows users to make decisions based on the trade - off between efficiency and solution size. 1.6m 1.4m 1.2m 1.0m 800k frequenc y (hz) 600k 400k 200k 0 0 20 40 rt resis t or (k?) 60 80 1 1636-039 figure 34 . switching frequency vs. rt resistor for channel 1 and channel 3, the freque ncy can be set to half the master switching frequency set by the rt pin. this setting can be selected by factory fuse. if the master switching frequency is less than 250 khz, this halving of the frequency for channel 1 or channel 3 is not recommended.
adp5053 data sheet rev. b | page 18 of 36 phas e shift the phase shift between channel 1 and channel 2 and between channel 3 and channel 4 is 180 . therefore, channel 3 is in phase with channel 1, and channel 4 is in phase with channel 2 (see figure 35 ). this phase shift maximizes the benefits of out - of - phase operation by reducing the input ripple current and lowering the ground noise. channel 2 channel 1 (? f sw optional) channel 4 swx 180 phase shift 0 reference 0 phase shift 180 phase shift channel 3 (? f sw optional) 1 1636-040 figure 35 . phase shift diagram, four buck regulators synchronization inpu t/output the switching frequenc y of the adp5053 can be synchronized to an external clock with a frequency range from 250 khz to 1.4 mhz. the adp5053 automatically de tects the presence of an external clock applied to the sync/mode pin, and the switching frequency transitions smoothly to the frequency of the external clock. when the external clock signal stops, the device automatically switches back to the internal cloc k and continues to operate. note that the internal switching frequency set by the rt pin must be programmed to a value that is close to the external clock value for effective synchronization; the suggested frequency difference is less than 15% in typical applications. the sync/mode pin can be configured as a synchronization clock output by factory fuse. regardless of the synchronization configuration method, the sync/mode pin generates a positive clock pulse with a 50% duty cycle and a frequency equal to t he internal switching frequency set by the rt pin. there is a short delay time (approximately 15% of t sw ) from the generated synchronization clock to the channel 1 switching node. figure 36 shows two adp5053 devices configured for frequency synchronization mode: one adp5053 device is configured as the clock output to synchronize another adp5053 device. it is recommended that a 100 k pull - up resistor be used to prevent logic errors when the sync/mode pin remains floating. adp5053 100k? vreg sync/mode sync/mode adp5053 1 1636-041 figure 36 . two adp5053 devices configured for synchronization mode in the configuration shown in figure 36 , the phase shift between channel 1 of the first adp5053 device and channel 1 of the second adp5053 device is 0 (see figure 37). ch3 5.00v b w ch1 2.00v b w ch2 5.00v b w m400ns a ch1 560mv 1 2 3 sw1 at first adp5053 sw1 at second adp5053 sync-out at first adp5053 1 1636-042 figure 37 . waveforms of two adp5053 devices operating in synchronization mode soft start the buck regulators in the adp5053 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. the soft start time is typically fixed at 2 ms for each buck regulator when the ss12 and ss34 pins are tied to vreg. to set the soft start time to a v alue of 2 ms, 4 ms, or 8 ms, connect a resistor divider from the ss12 or ss34 pin to the vreg pin and ground (see figure 38 ). this configuration may be required to accommodate a specific start - up sequence or an applic ation with a large output capacitor. leve l detec t or and decoder vreg t o p resis t or bot t om resis t or ss12 or ss34 adp5053 1 1636-043 figure 38 . level detector circuit for soft start use t he ss12 pin to program the soft start time and parallel operation for channel 1 and channel 2. use t he ss34 pin to program the soft start time for channel 3 and channel 4.
data sheet adp5053 rev. b | page 19 of 36 table 9 provides the required resister values to set the soft start time. table 9 . soft start time set by the ss12 and ss34 pins soft start time r top (k?) r b ot (k?) channel 1 channel 2 channel 3 channel 4 0 n/a 1 2 ms 2 ms 2 ms 2 ms 100 600 2 ms parallel 2 ms 4 ms 200 500 2 ms 8 ms 2 ms 8 ms 300 400 4 ms 2 ms 4 ms 2 ms 400 300 4 ms 4 ms 4 ms 4 ms 500 200 8 ms 2 ms 4 ms 8 ms 600 100 8 ms parallel 8 ms 2 ms n/a 1 0 8 ms 8 ms 8 ms 8 ms 1 n/a = not applicable. parallel operation the adp5053 supports two - phase parallel operation of channel 1 and channel 2 to provide a single output with up t o 8 a of current. take the following act ion s to configure channel 1 and channel 2 as a two - phase single output in parallel operation (see figure 39): ? use the ss12 pin to select parallel operation as specified in table 9 . ? leave the comp2 pin open. ? use the fb1 pin to set the output voltage. ? connect the fb2 pin to ground (fb2 is ignored). ? connect the en2 pin to ground (en2 is ignored). channel 1 buck regulator (4a) channel 2 buck regulator (4a) fb1 pvin1 v out (up to 8a) v in en1 en2 comp1 ss12 sw1 l1 fb2 sw2 l2 pvin2 comp2 vreg 1 1636-044 figure 39 . parallel o peration for channel 1 and channel 2 when operating channel 1 and channel 2 in the parallel configuration, configure the channels as follows: ? set the input voltages and current - limit settings for channel 1 and channel 2 to the same values. ? operate both cha nnels in forced pwm mode. current balance in parallel configuration is well regulated by the internal control loop. figure 40 shows the typical current balance matching in the parallel output configuration. 0 1 2 3 4 5 6 0 2 4 6 8 10 channe l current (a) t ot al output load (a) ch 1 ch 2 i d ea l 1 1636-045 figure 40 . current balance in parallel output configuration, v in = 12 v, v out = 1.2 v, f sw = 600 khz, fpwm mode startup with prechar ged output the buck regulators in the adp5053 include a precharged start - up feature to protect the low - side mosfets from damage during startup. if the output voltage is precharged before the regulator is turned on, the regulator prevents the reverse inductor current , which discharges the output capaci tor , until the internal soft start reference voltage exceeds the precharged voltage on the feedback (fbx) pin. current - limit protection the buck regulators in the adp5053 include peak current - lim it protection circuitry to limit the amount of positive current flowing through the high - side mosfet. the peak current limit on the power switch limits the amount of current that can flow from the input to the output. the programmable current - limit thresho ld feature allows for the use of small size inductors for low current applications. to configure the current - limit threshold for channel 1, connect a resistor from the dl1 pin to ground . t o configure the current - limit threshold for channel 2, connect anoth er resistor from the dl2 pin to ground. table 10 lists the peak current - limit threshold settings for channel 1 and channel 2. table 10 . peak current - limit threshold settings for channel 1 and ch annel 2 r ilim1 or r ilim2 typical peak current - limit threshold (a) floating 4.4 47 k? 2.63 22 k? 6.44 the buck regulators in the adp5053 include negative current - limit protection circuitry to limit certain amounts of negative current flowing through the low - side mosfet.
adp5053 data sheet rev. b | page 20 of 36 frequency foldback the buck regulators in the adp5053 include frequency foldback to prevent output current runaway when a hard short occurs on the output. implement f requency foldback as foll ows: ? if the voltage at the fbx pin falls below half the target output voltage, the switching frequency is reduced by half. ? if the voltage at the fbx pin falls again to below one - fourth the target output voltage, the switching frequency is reduced to half i ts current value, that is, to one - fourth of f sw . the reduced switching frequency allows more time for the inductor current to decrease but also increases the ripple current during peak current regulation. this results in a reduction in average current and prevents output current runaway. pulse skip mode under maximum duty cycle under maximum duty cycle conditions, frequency foldback maintains the output in regulation. if the maximum duty cycle is reached , for example, when the input voltage decreases , the p wm modulator skips every other pwm pulse, resulting in a switching frequency foldback of one - half. if the duty cycle increases further, the pwm modulator skips two of every three pwm pulses, resulting in a switching frequency foldback to one - third of the s witching frequency. frequency foldback increases the effective maximum duty cycle, thereby decreasing the dropout voltage between the input and output voltages. hiccup protection the buck regulators in the adp5053 include a hiccup mode for overcurrent protection (ocp). when the peak inductor current reaches the current - limit threshold, the high - side mosfet turns off and the low - side mosfet turns on until the next cycle. when hiccup mode is active, the overcurrent fault counter is incremented. if the overcurrent fault counter reaches 15 and overflows (indicating a short - circuit condition), both the high - side and low - side mosfets turn off. the buck regulator remains in hiccup mode for a period equal to seven soft start cycles and then attempts to restart from soft start. if the short - circuit fault has cleared, the regulator resumes normal operation; otherwise, it reenters hiccup mode after the soft start. hiccup protection is masked during the initial soft start cycle to enable startup of the buck regulator under heavy load conditions. for the buck regulator to recover from hiccup mode under heavy loads , careful design and proper component selection is required . to enable or disable h iccup protection f or all four buck regulators , use the factory fuse. when hiccup protection is disabled, the frequency foldback feature continues to be avail able for overcurrent protection. latch - off protection the buck regulators in the adp5053 have an optional latch - off mode to protect the device from serious problems such as short - circuit and overvoltage conditions. enable l atch - of f m ode by factory fuse. short - circuit latch - off mode short - circuit latch - off mode is enabled by factory fuse (on or off for all four buck regulators). when short - circuit latch - off mode is enabled and the protection circuit detects an overcurrent status after a soft start, the buck regulator enters hiccup mode and attempts to restar t. if after completing seven continuous restart attempts , the regulator remains in the fault condition, then the regulator is shut down. this shutdown (latch - off ) condition is clear ed only by reenabling the channel or by resetting the channel power supply. note that short - circuit latch - off mode does not work if hiccup protection is disabled. figure 41 shows the short - circuit latch - off detection function. output voltage time latch-off latch off this regulator short circuit detected by counter overflow pwrgd 7 t ss scp latch-off function enabled after 7 restart attempts attempt to restart 1 1636-046 figure 41. short - circuit latch - off dete ction overvoltage latch - off mode enable o vervoltage latch - off mode by factory fuse (on or off for all four buck regulators). the overvoltage latch - off threshold is 124% of the nominal output voltage level. when the output voltage exceeds this threshold, th e protection circuit detects the overvoltage status and the regulator shuts down. this shutdown (latch - off ) condition is cleared only by reenabling the channel or by resetting the channel power supply. figure 42 shows the overvoltage latch - off detection function. output voltage time latch off this regulator latch-off 124% nominal output 100% nominal output chx on 1 1636-047 figure 42. overvoltage latch - off detection
data sheet adp5053 rev. b | page 21 of 36 undervoltage lockout (uvlo) undervoltage lockout circuitry monitors the input voltage level of each buck regulator in the adp5053 . if any input voltage (pvinx pin) falls below 3.78 v (typical), the corresponding channel is turned off. t he soft start period initiate s a fter the input voltage rises above 4.2 v (typical), and setting the enx pin high enables the corresponding channel. note that a uvlo condition on channel 1 (pvin1 pin) has a higher priority than a uvlo condition on other channels, which means that the pvin1 supply must be available before other channels become operat ional . power - good function the adp5053 includes an open - drain power - good output (pwrgd pin) that becomes active high when the selected buck regulators are operating normally. by default, the pwrgd pin monitors the output voltage on channel 1. other channels can be configured to control the pwrgd pin when the adp5053 is ordered. a logic high on the pwrgd pin indicates that the regulated output voltage of the buck regulator is above 90.5% (typical) of its n om inal output. when the regulated output voltage of the buck regulator falls below 87.2% (typical ) of its nominal output for a delay time greater than approximately 50 s, the pwrgd pin goes l ow. the output of the pwrgd pin is the logical and of the internal pwrgx signals. an internal pwrgx signal must be high for a validation time of 1 ms before the pwrgd pin goes high; if one pwrgx signal fails, the pwrgd pin goes low with no delay. the chann els that control the pwrgd pin (channel 1 to channel 4) can be specified by factory fuse. the default pwrgd setting is to monitor the output of channel 1. thermal shutdown if the adp5053 junction temperature exceeds 150 c, the thermal shutdown (tsd) circuit turns off the ic except for the internal linear regulators. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. a 15 c hysteresis is included so that the adp5053 does not return to operation after thermal shutdown until the on - chip temperature falls below 135 c. when the device exits thermal shutdown, a soft start initiate s for each enabled channel. supervisory circuit the adp5053 provides microprocessor supply voltage supervision by controlling the reset input of the microprocessor. code e xecution errors are avoided during power - up, power - down, and brownout conditions by asserting a reset signal when the su pply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse after the supply voltage rises above the threshold. in addition, problems with microprocessor code execution can be monitored with a watchdog t i m e r. n ote that the supervisory circuitry activate s only when one of the enx pins of the four buck regulators is set high . reset output the adp5053 has an active low, open - drain reset output ( rsto ) . this output requires an external pull - up resistor to connect the reset output to a voltage rail no higher t han 6 v. the resistor must comply with the logic low and logic high voltage level requirements of the microprocessor while also supplying input current and leakage paths to the rsto pin. a 10 k? resistor is adequate in most situations. the reset output assert s when the monitored rail is below the threshold (v th ), and when wdi is not serviced within the watchdog timeout period (t wd ). t he rsto pin remains asserted for the durati on of the reset active timeout period (t rp ) after v cc rises above the reset threshold or after the watchdog timer times out. there are f our options are available for the reset active timeout period (t rp ) via the factory fuse: 1.4 ms, 28 ms, 200 ms (default ) , or 1600 ms. figure 43 illustrates th e behavior of the rsto output, assum ing that v out2 is selected as the rail to be monitored and it supplies the external pull - up connected to the rsto output. t r p t rd v out2 v th v th v out2 1v 0v 0v v out2 1 1636-048 rsto figure 43 . reset timing diagram the adp5053 has a dedicated sensing input pin ( vth ) to m on it or the supply rail. the reset threshold at the vth input is typically 0.5 v. to monitor a voltage greater than 0.5 v, connect a resistor divider network to the device. do not allow the vth input to float or to be grounded . i nstead , connect the vth input to a supply voltage greater than its specified threshold voltage (v th ) . a dd a small capacitor on the vth pin to improve noise rejection and false reset generation. when monitoring the input voltage, if the selected voltage falls below the uvlo level , the reset output ( rsto ) assert s low with the delay time (t rd ) . the reset output is then kept low to restart the processor .
adp5053 data sheet rev. b | page 22 of 36 watchdog input the adp5053 features a watchdog timer that monitors microprocessor activity. a timer circuit is cleared with every low to high or high to low logic transition on the watchdog input pin (wdi), which detects pulses as short as 80 ns. if the timer proceeds through the preset watchdog timeout period (t wd ), reset is asserted. the microprocessor is required to toggle the wdi pin to avoid being reset. therefore, failure of the microprocessor to toggle the wdi pin within the timeout period indicates a code execution error, and the reset pulse generated restarts the micro-processor in a known state. four options are available for the watchdog timeout period via the factory fuse: 6.3 ms, 102 ms, 1600 ms (default), or 25.6 sec. in addition to the logic transition on the wdi pin, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on v out2 . when a reset is asserted, the watchdog timer clears, and the timer does not begin counting again until the reset is deasserted. disable the watchdog timer by leaving wdi floating or by three-stating the wdi driver. figure 44 shows the watchdog timing diagram. v th v out2 v out2 wdi 1v 0v 0v 0v v out2 v out2 t rp t rp t wd 11636-049 rsto figure 44. watchdog timing diagram manual reset input the adp5053 features a manual reset input ( mr pin, active low) with two operation modes: processor manual reset mode or power on/off switch mode. the default setting is the processor manual reset mode; however, mr operation mode selection can be configured by factory fuse. the mr input has an internal 55 k pull-up resistor so that the input remains high when unconnected. to generate a reset, connect an external push-button switch between mr and ground. noise immunity is provided on the mr input, and fast, negative going transients of up to 100 ns (typical) are ignored. a 0.1 f capacitor between mr and ground provides additional noise immunity. processor manual reset mode in processor manual reset mode, when mr is driven low, the reset output is asserted. when mr transitions from low to high, the reset remains asserted for the duration of the reset active timeout period (t rp ) before deasserting. figure 45 shows the behavior of the mr pin in processor manual reset mode. mr mr externally driven low rsto v cc t rp t rp v th v th 11636-050 figure 45. mr timing diagram in processor reset mode power on/off switch mode in power on/off switch mode, when mr is driven low for more than 4 sec, all channels in the adp5053 shut down, and the internal control registers reset. in this shutdown standby condition, if mr is driven low for 500 ms again, all channels in the adp5053 restart according to the individual enx pin status. figure 46 shows the mr timing diagram in power on/off switch mode. to prepare for automatic startup, clear the mr shutdown condition by pulling down all external enx pins. 11636-051 500ms 4s 1s blanking t rp t rp sequence start-up sequence start-up mr shutdown by 4s mr timer mr shutdown mode force rsto low in shutdown mode restart all power by 500ms mr timer mr (used as on/off switch) vout1 to vout4 pvinx/enx rsto figure 46. mr timing diagram in power on/off switch mode
data sheet adp5053 rev. b | page 23 of 36 appli cations information adi sim p ower design tool the adp5053 is supported by the adisimpower ? design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic and bill of materials and to calculate performance in minutes. adisimpower optimize s designs for cost, area, efficiency, and device count while taking into consideration the operating conditions and limitations of the ic and all real external components. access t he adisimpower tool at www.analog.com/ adisimpower ; the user can request an unpopulated board through the tool. programming the adju stable output voltage the output voltage of the adp5053 is externally set by a resistive voltage divi der from the output voltage to the fbx pin. to limit the degradation of the output voltage accuracy due to feedback bias current, ensure that the bottom resistor in the divider is not too large ; a value of less than 50 k ? is recommended. the equation for the output voltage setting is v out = v ref (1 + ( r top / r bot )) where: v out is the output voltage. v ref is the feedback reference voltage ( 0.8 v for channel 1 to channel 4 ) . r top is the feedback resistor from v out to fb x . r bot is the feedback resistor from fb x to ground. no resistor divider is required in the fixed output options. if a different fixed output voltage is required, contact your local analog devices sales or distribution representative. voltage conversion l im itations for a given input voltage, upper and lower limitations on the output voltage exist due to the minimum on time and the minimum off time. the minimum output voltage for a given input voltage and switching frequency is limited by the minimum on time. the minimum on time for channel 1 and channel 2 is 117 ns (typical) ; the minimum on time for channel 3 and channel 4 is 90 ns (typical). the minimum on time increases at higher junction temperatures. note that in forced pwm mode, channel 1 and channel 2 c an potentially exceed the nominal output voltage when the minimum on time limit is exceeded. careful switching frequency selection is required to avoid this problem. calculate t he minimum output voltage in continuous conduction mode (ccm) for a given i nput voltage and switching frequency using the following equation: v out_ min = v in t min_ on f sw ? ( r dson1 ? r dson2 ) i out_ min t min_ on f sw ? ( r dson2 + r l ) i o u t_ m i n (1) where: v out_ min is the minimum output voltage. t min_ on is the minimum on time. f sw is the switching frequency. r dson1 is the on resistance of the high - side mosfet . r dson2 is the on resistance of the low - side mosfet . i out_ min is the minimum output current. r l is the resistance of the output inductor. the maximum output voltage for a gi ven input voltage and switching frequency is limited by the minimum off time and the maximum duty cycle. note that the frequency foldback feature helps to increase the effective maximum duty cycle by lowering the switching frequency, thereby decreasing the dropout voltage between the input and output voltages (see the frequency foldback section). calculate t he maximum output voltage for a given input voltage and switching frequency using the following equation: v out _max = v in (1 ? t min_ off f sw ) ? ( r dson1 ? r dson2 ) i out_ max (1 ? t m in _ of f f sw ) ? ( r dson2 + r l ) i o u t _ ma x (2) where: v out_ max is the maximum output voltage. t min_ off is the minimum off time. f sw is the switching frequency. r dson1 is the on resistance of th e high - side mosfet. r dson2 is the on resistance of the low - side mosfet. i out_ max is the maximum output current. r l is the resistance of the output inductor. as shown in equation 1 and equation 2, reducing the switching frequency eases the minimum on time a nd off time limitations. current - limit setting the adp5053 has three selectable current - limit thresholds for channel 1 and channel 2. make sure that the selected current - limit value is larger tha n the peak current of the inductor, i peak . see table 10 for the current - limit configuration for channel 1 and channel 2.
adp5053 data sheet rev. b | page 24 of 36 soft start setting the buck regulators in the adp5053 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. to set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a resistor divider from th e ss12 or ss34 pin to the vreg pin and ground (see the soft start section). inductor selection the input voltage, output voltage, inductor ripple current, and switching frequency determine the inductor value. usin g a small inductor value yields faster transient response but degrades efficiency due to the larger inductor ripple current. using a large inductor value yields a smaller ripple current and better efficiency but results in slower transient response. thus, a trade - off is required between transient response and efficiency. as a guideline, the inductor ripple current, i l , is typically set to a value from 30% to 40% of the maximum load current. calculate t he inductor value using the following equation: l = [( v i n ? v out ) d ]/( i l f sw ) where: v in is the input voltage. v out is the output voltage. d is the duty cycle ( d = v out / v in ). i l is the inductor ripple current. f sw is the switching frequency. the adp5053 has internal slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is greater than 50%. because the internal current sense signal is required, the inductor value must not be larger than 10 h for c hannel 1 and channel 2 or 22 h for channel 3 and chan nel 4. calculate t he peak inductor current using the following equation: i peak = i out + ( i l /2) the saturation current of the inductor must be larger than the peak inductor current. for ferrite core inductors with a fast saturation characteristic, to prevent the inductor from becoming saturated by ensuring that the saturation current rating of the inductor is higher than the current - limit threshold of the buck regulator. calculate t he rms current of the inductor using the following equation: 12 2 2 l out rms i i i ? + = table 11 . recommended inductors vendor part no. v a l ue (h) i sat (a) i rms (a) dcr (m?) size (mm) coilcraft xfl4020 - 102 1.0 5.4 11 10.8 4 4 xfl4020 - 222 2.2 3.7 8.0 21.35 4 4 xfl4020 - 332 3.3 2.9 5.2 34.8 4 4 xfl4020 - 472 4.7 2.7 5.0 52.2 4 4 xal4030 - 682 6.8 3.6 3.9 67.4 4 4 xal4040 - 103 10 3.0 3.1 84 4 4 xal6030 - 102 1.0 23 18 5.62 6 6 xal6030 - 222 2.2 15.9 10 12.7 6 6 xal6030 - 332 3.3 12.2 8.0 19.92 6 6 xal6060 - 472 4.7 10.5 11 14.4 6 6 xal6060 - 682 6.8 9.2 9.0 18.9 6 6 toko fdv0530 - 1 r0 1.0 11.2 9.1 9.4 6.2 5.8 fdv0530 - 2 r2 2.2 7.1 7.0 17.3 6.2 5.8 fdv0530 - 3 r3 3.3 5.5 5.3 29.6 6.2 5.8 fdv0530 - 4 r7 4.7 4.6 4.2 46.6 6.2 5.8 output capacitor sel ection the selected output capacitor affects both the output voltage ripple and the loop dynamics of the regulator. for example, during load step t ransients on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop can ramp up the inductor current, causing an undershoot of the output voltage. calculate t he output capacitance required to meet the undershoot (voltage droop) requirement using the following equation: ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = k uv is a factor (typically set to 2). i step is the load step. v out_uv is the allowable undershoot on the output voltage. another example of the effect of the output capacitor on the loop dynamics of the regulator is when the load is suddenly removed from the output and the energy stored in t he inductor rushes into the output capacitor, causing an overshoot of the output voltage. calculate t he output capacitance required to meet the oversho ot requirement using the following equation: ( ) out out_ov out step ov ov out v v v l i k c ? ? + ? = k ov is a factor (typically set to 2). i step is the load step. v out_ov is the allowable overshoot on the output voltage.
data sheet adp5053 rev. b | page 25 of 36 the equivalent series resistance ( esr ) of the output capacitor and its capacitance value determine the output voltage ripple. use the following equations to select a ca pacitor that can meet the output ripple requirements: ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ where: i l is the inductor ripple current. f sw is the switching frequency. v out_ripple is the allowable output voltage ripple. r esr is the equivalent serie s resistance of the output capacitor. select the largest output capacitance given by c out_uv , c out_ ov , and c out_ripple to meet both load transient and output ripple requirements. the voltage rating of the selected output capacitor must be greater than the output voltage. determine t he minimum rms current rating of the output capacitor by the following equation: 12 _ l rms c i i out ? = input capacitor sele ction the input decoupling capacitor attenuates high frequency noise on the input and acts as an energy r eservoir. use a ceramic capacitor and place it near the pvinx pin. keep t he loop composed of the input capacitor, the high - side nfet, and the low - side nfet as small as possible. the voltage rating of the input capacitor must be greater than the maximum inp ut voltage. ensure that the rms current rating of the input capacitor is larger than the following equation: ( ) d d i i out rms c in ? = 1 _ where d is the duty cycle ( d = v out / v in ). low - side power device se lection channel 1 and channel 2 include integrated low - sid e mosfet drivers that drive low - side n - channel mosfets (nfets). the selection of the low - side n - channel mosfet affects the performance of the buck regulator. the selected mosfet must meet the following requirements: ? drain - to - source voltage (v ds ) must be hi gher than 1.2 v in . ? drain current (i d ) must be greater than 1.2 i limit_max , where i limit_ max is the selected maximum current - limit threshold. ? the selected mosfet can be fully turned on at v gs = 4.5 v. ? total gate charge (qg at v gs = 4.5 v) must be less t han 20 nc. lower qg characteristics provide higher efficiency. when the high - side mosfet is turned off, the low - side mosfet supplies the inductor current. for low duty cycle applications, the low - side mosfet supplies the current for most of the period. t o achieve higher efficiency, it is important to select a mosfet with low on resistance. the power conduction loss for the low - side mosfet can be calculated using the following equation: p fet_ low = i out 2 r dson (1 ? d ) where: r dson is the on resistance of the low - side mosfet. d is the duty cycle ( d = v out / v in ). table 12 lists recommended dual mosfets for various current - limit settings. ensure that the mosfet can handle therm al dissipation due to power loss. table 12 . recommended dual mosfets vendor part no. v ds (v) i d (a) r dson (m?) qg (nc) size (mm) ir irfhm8363 30 10 20.4 6.7 3 3 irlhs6276 20 3.4 45 3.1 2 2 fairchild fdma1024 20 5.0 54 5.2 2 2 fdmb3900 25 7.0 33 11 3 2 fdmb3800 30 4.8 51 4 3 2 fdc6401 20 3.0 70 3.3 3 3 vishay si7228dn 30 23 25 4.1 3 3 si7232dn 20 25 16.4 12 3 3 si7904bdn 20 6 30 9 3 3 si5906du 30 6 40 8 3 2 si5908dc 20 5.9 40 5 3 2 sia906edj 20 4.5 46 3.5 2 2 aos aon7804 30 22 26 7.5 3 3 aon7826 20 22 26 6 3 3 ao6800 30 3.4 70 4.7 3 3 aon2800 20 4.5 47 4.1 2 2 programming the uvlo input use t he precision enable input to program the uvlo threshold of the input voltage, as show n in figure 33 . to limit the degradation of th e input voltage accuracy due to the internal 1 m? pull - down resistor tolerance, ensure that the bottom resistor in the divider is not too large ; a value of less than 50 k? is recommended. the precision turn - on threshold is 0.8 v. calculate t he resistive voltage divider for the programmable v in start - up voltage as follows: ? ? ? ? ? ? ? ? m 1 + m 1 + )) v/ (0.8 + na (0.8 = bot_en bot_en top_en bot_en in_startup r r r r v r r top_ en is the resistor from v in to en. r bot_ en is the resistor from en to ground.
adp5053 data sheet rev. b | page 26 of 36 compensation compone nts design for the peak current mode control architecture, simplify the power stage as a voltage controlled current source that supplies current to the output capacitor and load resistor. the simplified loop is composed of one domain pole and a zero contributed by the output capacitor esr. the control - to - output transfer function is shown in the following equations: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = = p z vi comp out vd f s f s r a s v s v s g 2 1 2 1 ) ( ) ( ) ( out esr z c r f = 2 1 ( ) out esr p c r r f + = 2 1 where: a vi = 10 a/v for channel 1 or chann el 2, and 3.33 a/v for channel 3 or channel 4. r is the load resistance. s = the frequency domain factor. r esr is the equivalent series resistance of the output capacitor. c out is the output capacitance. the adp5053 uses a transconductance amplifier as the error amplifier to compensate the system. figure 47 shows the simplified peak current mode control small signal circuit. r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out 1 1636-052 figure 47 . simplified peak current mode control small signal circuit the compensation components, r c and c c , contribute a zero; r c and the optional c cp contribute an optional pole. the closed - loop transfer equation is as follows: ) ( 1 1 ) ( s g s c c c c r s s c r c c g r r r s t vd cp c cp c c c c cp c m top bot bot v ? ? ? ? ? ? ? ? + + + + ? + = determine the cross frequency (f c ). generally, f c is between f sw /12 and f sw /6. 2. calculate r c using the following equation : vi m c out out c a g f c v r = v 8 . 0 2 3. place the compensation zero at the domain pole (f p ). calculate c c using the following equation: ( ) c out esr c r c r r c + = c cp is optional. it can be used to cancel the zero caused by the esr of the output capacitor. calculate c cp using t he following equation: c out esr cp r c r c = power dissipation the total power dissipation in the adp5053 simplifies to p d = p buck 1 + p buck 2 + p buck 3 + p buck 4 buck regulator power dissipation t he power dissipation (p loss ) for each buck regulator includes power switch conduction losses (p cond ), switching losses (p sw ), and transition losses (p tran ). other sources of power dissipation exist, but these sources are generally less significant at the h igh output currents of the application thermal limit. use the following equation to estimate the power dissipation of the buck regulator: p loss = p cond + p sw + p tran power switch conduction loss (p cond ) power switch conduction losses are caused by the flow of output current through both the high - side and low - side power switches, each of which has its own internal on resistance (r dson ). use the following equation to estimate the power switch conduction loss: p cond = ( r dson_hs d + r dson_ls (1 ? d )) i out 2 where: r dson_hs is the on resistance of the high - side mosfet. r dson_ls is the on resistance of the low - side mosfet. d is the duty cycle ( d = v out / v in ).
data sheet adp5053 rev. b | page 27 of 36 switching loss (p sw ) switching losses are associated with the current drawn by the driver to turn the power devices on and off at the switching frequency. each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. use the following equation to estimate the switching loss: p sw = ( c gate_ hs + c gate_ ls ) v in 2 f sw where: c g ate _ hs is the gate capacitance of the high - side mosfet. c g ate _ l s is the gate capacitance of the low - side mosfet. f sw is the switching frequency. transition loss (p tran ) tran sit i on losses occur because the high - side mosfet cannot turn on or off instantaneously. during a switch node transition, the mosfet provides all the inductor current. the source - to - drain voltage of the mosfet is half the input voltage, resulting in power loss. transition losses increase with both load and input voltage and occur twice for each switching cycle. use the following equation to estimate the transition loss: p tran = 0.5 v in i out ( t r + t f ) f sw where: t r is the rise time of the switch node. t f is the fall time of the switch node. thermal shutdown channel 1 and channel 2 store the value of the inductor current only during the on time of the internal high - side mosfet. therefore, a small amount of power (as well as a small amount of input rms curre nt) dissipate s inside the adp5053 , which reduces thermal constraints. however, when channel 1 and channel 2 are operating under maximum load with high ambient temperature and high duty cycle, the input rms current can become very large and cause the junction temperature to exceed the maximum junction temperature of 125c. if the junction temperature exceeds 150c, the regulator enters thermal shutdown and recovers when the junction temperature fal ls below 135c. junction temperature the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation: t j = t a + t r where: t j i s the junction temperature. t a is the ambient temperature. t r is the rise in temperature of the package due to power dissipation. the rise in temperature of the package is directly proportional to the power dissipation in the package. the proportionality c onstant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: t r = ja p d where: t r is the rise in temperature of the package. ja is the thermal resistance from the junction of the die to the ambient temperature of the package (see table 6 ). p d is the power dissipation in the p ackage. an important factor to consider is that the thermal resistance value is based on a 4 - layer, 4 inch 3 inch pcb with 2.5 oz. of copper, as specified in the jedec standard, whereas real - world applications may use pcbs with different dimensions and a different number of layers. it is important to maximize the amount of copper used to remove heat from the device. copper exposed to air dissipates heat better than copper used in the inner layers. connect the exposed pad to the ground plane with several v ias.
adp5053 data sheet rev. b | page 28 of 36 design example this section provides an example of the step - by - step design procedures and the external components required for channel 1. table 13 lists the design requirements for this specific example. table 13 . example design requirements for channel 1 parameter specification input voltage v pvin1 = 12 v 5% output voltage v ou t1 = 1.2 v output current i ou t1 = 4 a output ripple v out1_ripple = 12 mv in ccm mode load transient 5% at 20% to 80% load transient, 1 a/s although this example shows step - by - step design procedures for channel 1, the procedures apply to all other buck regulator channels (channel 2 to channel 4). settin g the switching freq uency the first step is to determine the switching frequency for the adp5053 design. in general, higher switching frequencies produce a smaller solution size due to the lower component values required, whereas lower switching frequencies result in higher conversion efficiency due to lower switching losses. the switching frequency of the adp5053 can be set to a value f rom 250 khz to 1.4 mhz by connecting a resistor from the rt pin to ground. the selected resistor allows the user to make decisions based on the trade - off between efficiency and solution size. (for more information, see the oscillator section.) however, the highest supported switching frequency must be assessed by checking the voltage conversion limitations enforced by the minimum on time and the minimum off time (see the vo l t age conversion limitations section). in this design example, a switching frequency of 600 khz achieve s a good combination of small solution size and high conversion efficiency. to set the switching frequency to 600 khz, use the following equation to calcu late the resistor value, r rt : r rt (k ? ) = [14,822/ f sw (khz)] 1. 081 therefore, select standard resistor r rt = 31.6 k. setting the output v oltage select a 10 k ? bottom resistor (r bot ) and then calculate the top feedback resistor using the following equation: r bot = r top ( v ref /( v out ? v ref )) w here: v ref is 0.8 v for channel 1. v out is the output voltage. to set the output voltage to 1.2 v, choose the following resistor values: r top = 4.99 k and r bot = 10 k. setting the current limit for 4 a output current operation, the typical peak current l imit is 6 .44 a. for this example, choose r ilim1 = 22 k? (see table 10 ). for more information, see the current - limit protection section. selecting the induct or the peak - to - peak inductor ripple current, i l , is set to 35% of the maximum output current. use the following equation to estimate the value of the inductor: l = [( v in ? v out ) d ]/( i l f sw ) where: v in = 12 v. v out = 1.2 v. d is the duty cycle ( d = v out / v in = 0.1). i l = 35% 4 a = 1.4 a. f sw = 600 khz. the resulting value for l is 1.28 h. the closest standard inductor value is 1.5 h; therefore, the inductor ripple current, i l , is 1.2 a. the peak inductor current is calculated using the following equation: i peak = i ou t + ( i l /2) the calculated peak current for the inductor is 4.6 a. calculate t he rms current of the inductor using the following equation: 12 2 2 l out rms i i i ? + =
data sheet adp5053 rev. b | page 29 of 36 selecting the output capacitor the output capacitor must meet the output voltage ripple and load transient requirements. to meet the output voltage ripple requirement, use the following equations to calculate the e sr and capacitance: ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ the calculated capacitance, c out_ripple , is 20.8 f, and the calculated r esr is 10 m. to meet the 5% overshoot and undershoot requirements, use the following equations to calculate the cap acitance: ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = ( ) out out_ov out step ov ov out v v v l i k c ? ? + ? = selecting the low - side mosfet a low r dson n - channel mosfet must be selected for high efficiency solutions. the mosfet breakdown voltage (v ds ) must be greater than 1.2 v in , and the drain current must be greater than 1.2 i limit_ max . it is recommended that a 20 v, dual n - channel mosfet , such as the si7232dn from vishay , be used for both channel 1 and channel 2. the r dson of the si7232dn at 4.5 v driver voltage is 16.4 m, and the total gate charge is 12 nc. designing the compen sation network for better load transient and stability performance, set the cross frequency, f c , to f sw /10. in this example, f sw is set to 600 khz; therefore, f c is set to 60 khz. for the 1.2 v output rail, the 47 f ceramic output capacitor has a derated value of 40 f. k 14.4 a/v 10 s 470 v 0.8 khz 60 f 40 3 v 1.2 2 = = c r ( ) = + = c c pf 3 144 f 4 3 1 = = cp c cs stdrd mpts r c 1 d c c 2 f c cp s pt fgr 4 ss t bd pt fr t 12 v tpt r t rss fr s 2 hz d t ps mrg s fg r 4 ss t d trst vf rm 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 120 ?180 ?150 ?120 ?90 ?60 ?30 0 30 60 90 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 62khz phase margin: 58 1 1636-053 figure 48 . bode plot for 1.2 v output ch1 50.0m v b w &+$? b w m200s a ch4 2.32a 1 4 v out i out 1 1636-054 figure 49 . 0.8 a to 3.2 a load transient for 1.2 v output selecting the soft s tart time the soft start feature allows the output voltage to ramp up in a control led manner, eliminating output voltage overshoot during soft start and limiting the inrush current. use t he ss12 pin to program a soft start time of 2 ms, 4 ms, or 8 ms and to configure parallel operation of channel 1 and channel 2. for more information, s ee the soft start section and table 9 . selecting the input capacitor for the input capacitor, select a ceramic capacitor with a minimum value of 10 f; place the input capacit or near to the pvin1 pin. in this example, one 10 f, x5r, 25 v ceramic capacitor is recommended.
adp5053 data sheet rev. b | page 30 of 36 recommended external components table 14 lists the recommended external components for 4 a applications used with channel 1 and channel 2 of the adp5053 . table 15 lists the recommended external components for 1.2 a applications used with channel 3 and channel 4. tabl e 14 . recommended external components for typical 4 a applications, channel 1 and channel 2 (1% output ripple, 7.5% tolerance at ~60% step transient) f sw (khz) i out (a) v in (v) v out (v) l (h) c out (f) r top (k ? ) r bot (k ? ) r c (k ? ) c c (pf) dual fet 300 4 12 (or 5) 1.2 3.3 2 100 1 4.99 10 10 4700 si7232dn 12 (or 5) 1.5 3.3 2 100 1 8.87 10.2 10 4700 si7232dn 12 (or 5) 1.8 3.3 3 47 2 12.7 10.2 6.81 4700 si7232dn 12 (or 5) 2.5 4.7 3 47 2 21.5 10.2 10 4700 si7232dn 12 (o r 5) 3.3 6.8 3 47 2 31.6 10.2 10 4700 si7232dn 12 5.0 6.8 47 3 52.3 10 4.7 4700 si7232dn 600 4 12 (or 5) 1.2 1.5 2 47 2 4.99 10 10 2700 si7232dn 12 (or 5) 1.5 1.5 2 47 2 8.87 10.2 10 2700 si7232dn 12 (or 5) 1.8 2.2 2 47 2 12.7 10.2 10 2700 si7 232dn 12 (or 5) 2.5 2.2 2 47 2 21.5 10.2 10 2700 si7232dn 12 (or 5) 3.3 3.3 2 47 2 31.6 10.2 15 2700 si7232dn 12 5.0 3.3 47 3 52.3 10 10 2700 si7232dn 1000 4 5 1.2 1.0 2 47 2 4.99 10 15 1500 si7232dn 5 1.5 1.0 2 47 2 8.87 10.2 15 1500 si723 2dn 12 (or 5) 1.8 1.0 47 2 12.7 10.2 10 1500 si7232dn 12 (or 5) 2.5 1.5 47 2 21.5 10.2 10 1500 si7232dn 12 (or 5) 3.3 1.5 47 2 31.6 10.2 10 1500 si7232dn 12 5.0 2.2 47 3 52.3 10 15 1500 si7232dn 1 100 f capacitor: murata grm31cr60j107me39 (6.3 v , x5r, 1206). 2 47 f capacitor: murata grm21br60j476me15 (6.3 v, x5r, 0805). 3 47 f capacitor: murata grm31cr61a476me15 (10 v, x5r, 1206). table 15 . recommended external components for typical 1.2 a applications, channel 3 and ch annel 4 (1% output ripple, 7.5% tolerance at ~60% step transient) f sw (khz) i out (a) v in (v) v out (v) l (h) c out (f) r top (k ? ) r bot (k ? ) r c (k ? ) c c (pf) 300 1.2 12 (or 5) 1.2 10 2 22 1 4.99 10 6.81 4700 12 (or 5) 1.5 10 2 22 1 8.87 10.2 6.81 4700 12 (or 5) 1.8 15 2 22 1 12.7 10.2 6.81 4700 12 (or 5) 2.5 15 2 22 1 21.5 10.2 6.81 4700 12 (or 5) 3.3 22 2 22 1 31.6 10.2 6.81 4700 12 5.0 22 22 2 52.3 10 6.81 4700 600 1.2 12 (or 5) 1.2 4.7 22 1 4.99 10 6.81 2700 12 (or 5) 1.5 6.8 22 1 8.87 10.2 6.81 2700 12 (or 5) 1.8 6.8 22 1 12.7 10.2 6.81 2700 12 (or 5) 2.5 10 22 1 21.5 10.2 6.81 2700 12 (or 5) 3.3 1 0 22 1 31.6 10.2 6.81 2700 12 5.0 10 22 2 52.3 10 6.81 2700 1000 1.2 5 1.2 2.2 22 1 4.99 10 10 1800 12 (or 5) 1.5 3.3 22 1 8.87 10.2 10 1800 12 (or 5) 1.8 4.7 22 1 12.7 10.2 10 1800 12 (or 5) 2.5 4.7 22 1 21.5 10.2 10 1800 12 (or 5) 3.3 6.8 22 1 3 1.6 10.2 10 1800 12 5.0 6.8 22 2 52.3 10 15 1800 1 22 f capacitor: murata grm188r60j226mea0 (6.3 v, x5r, 0603). 2 22 f capacitor: murata grm219r61a226mea0 (10 v, x5r, 0805).
data sheet adp5053 rev. b | page 31 of 36 circuit board layout recommendations effective circuit board layout is ess ential to obtain the best perfor mance from the adp5053 (see figure 51 ). poor layout can affect the regulation and stability of the device , as well as the electromagnetic interference (emi) and electromagnetic compatibility (emc) performance. refer to the following guidelines for the most effective pcb layout. ? place the input capacitor, inductor, mosfet, output capacitor, and bootstrap capacitor near to the ic. ? use short, thick traces to connect the input capacitors to the pvinx pins, and use dedicated power ground to connect the input and output capacitor grounds to minimize the connection length. ? use several high current vias, if required, to connect pvinx , pgndx, and swx to other power planes. ? use short, thick traces to connect the inductors to the swx pins and the output capacitors. ? ensure that the high current loop traces are as short and wide as possible. figure 50 shows the high current path. ? maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. ? use a ground plane with several vias connect ed to the com ponent side ground t o further reduce noise interference on sensitive circuit nodes. ? place the decoupling capacitors near to the vreg and vdd pins. ? place the frequency setting resistor near to the rt pin. ? place the feedback resistor divider near to the fbx pin. in addition, ke ep the fbx traces away from the high current traces and the switch node to avoid noise pickup. ? use 0402 or 0603 size resistors and capacitors to achieve the smallest possible footprint solution on boards where space is limited. v in v out pvinx enx pgnd bstx swx adp5053 dlx fbx 1 1636-055 figure 50 . typical circuit with high current traces shown in gray a d p 5 0 5 3 a d p 5 0 5 3 l 1 l 3 l 4 d u a l m o s f e t l 2 l 1 l 2 v o u t 4 v o u t 3 v o u t 2 v o u t 1 1 1636-056 figure 51 . typical pcb layout
adp5053 data sheet rev. b | page 32 of 36 typical application circuits vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 2.2h 4.7h 6.8h 10h l2 5v reg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 vreg l3 bst3 sw3 fb3 pgnd3 l4 bst4 sw4 fb4 pgnd4 vreg vreg pvin1 comp1 en1 pvin2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 c2 10f 4.7nf 4.7k? 31.6k? 2.7nf 6.81k? 2.7nf 6.81k? c1 1.0f c4 47f c3 0.1f c5 10f c6 0.1f c8 10f c9 0.1f c10 22f c11 10f c12 0.1f c13 22f 12v vout1 vout2 vout3 1.2v/2.5a vcore i/o 1.5v/1.2a 4.0v to 4.5v/1.2a (dvs) vout4 5v reg exposed pad ss12 c0 1.0f vdd watchdog and reset wdi vth adp5053 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) c7 47f comp2 4.7nf 4.7k? vreg 3.3v/2.5a vout1 10k? 10k? 10k? sia906edj (46m?) 1 1636-058 ddr termination ldo ddr memory processor rfpa rf transceiver rsto mr figure 52 . typical femtocell application, 600 khz switching frequency , fixed output model
data sheet adp5053 rev. b | page 33 of 36 vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 1.5h 2.2h 6.8h 10h l2 5v reg sync/mode fb1 rt bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 vreg l3 bst3 sw3 fb3 pgnd3 l4 bst4 sw4 fb4 pgnd4 vreg vreg pvin1 comp1 en1 pvin2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 c2 10f 4.7nf 10k? 31.6k? 2.7nf 6.81k? 2.7nf 6.81k? c1 1.0f c4 47f c3 0.1f c5 10f c6 0.1f c8 10f c9 0.1f c10 22f c11 10f c12 0.1f c13 22f 12v vout1 vout2 vout3 1.2v/4a vcore 1.5v/1.2a 3.3v/1.2a vout4 5v reg exposed pad ss12 c0 1.0f vdd watchdog and reset wdi vth adp5053 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) c18 47f c7 47f c19 47f comp2 4.7nf 10k? vreg reset gpio rsto wdi 2.5v/4a vout1 rsto 10k? 11k? 10k? 10.2k? 10.2k? 31.6k? 8.87k? 4.99k? 10k? si7232dn (16.4m?) ddr memory i/o bank 3 flash memory processor bank 2 i/os auxiliary voltage fpga bank 1 bank 0 1 1636-059 ddr termination ldo 22k? 22k? mr figure 53 . typical fpga application, 600 khz switching frequency, adjustable output model
adp5053 data sheet rev. b | page 34 of 36 vreg vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 1.5h 1.5h 6.8h 10h l2 5v reg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 vreg l3 bst3 sw3 fb3 pgnd3 l4 bst4 sw4 fb4 pgnd4 vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 c2 10f 4.7nf 10k? 100k? 600k? 31.6k? 2.7nf 6.81k? 2.7nf 6.81k? c1 1.0f c4 100f c3 0.1f c5 10f c6 0.1f c8 10f c9 0.1f c10 22f c11 10f c12 0.1f c13 22f 12v vout1 vout3 1.2v/8a 1.5v/1.2a 3.3v/1.2a vout4 22k? 22k? 5v reg exposed pad ss12 c0 1.0f vdd watchdog and reset vth wdi adp5053 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) c18 100f vreg mr rsto 4.99k? 10k? 10k? 51k? 10k? 8.87k? 31.6k? 10.2k? 10.2k? si7232dn (16.4m?) 1 1636-060 figure 54 . typical channel 1/channel 2 parallel output application, 600 khz switching frequency, adjustable output model
data sheet adp5053 rev. b | page 35 of 36 factory default opti ons table 16 lists the factory default options programmed into the adp5053 when the device is ordered (see the ordering guide ). to order the device with options other than the default options, contact your local analog devices sales or distribution representative . table 16 . factory default options option default value channel 1 output voltage 0.8 v adjustable output channel 2 output voltage 0.8 v adjustable output channel 3 output voltage 0.8 v adjustable output channel 4 output voltage 0.8 v adjustable output pwrgd p in (pin 20) o utput monitor channel 1 output output discharge function enabled for all four buck regulators switching f requency on channel 1 1 switching frequency set by the rt pin switching f requency on channel 3 1 switching frequency set by the rt pin sync/mode p in (pin 43) f unction forced pwm/automatic pwm/psm mode setting with the ability to synchronize to an external clock hiccup p rotection enabled for overcurrent events short - circuit latch - off function disabled for output short - circuit event s overvoltage latch - off function disabled for output overvoltage events reset timeout period 200 ms watchdog timeout period 1.6 sec m anual reset input m ode processor manual reset mode
adp5053 data sheet rev. b | page 36 of 36 outline dimensions compliant to jedec standards mo-220- wkkd-4 . for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 0.50 bsc bot t om view top view pin 1 indic at or 48 13 24 36 37 pin 1 indic at or 5.70 5.60 sq 5.50 0.50 0.40 0.30 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 02-29-2016- a 7.10 7.00 sq 6.90 0.20 min 5.50 ref end view exposed pa d pkg-004452 figure 55 . 48 - lead lead frame chip scale package [lfcsp_wq] 7 mm 7 mm body, very very thin quad (cp - 48- 13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option 2 adp5053 acpz - r7 ?40c to +125c 48 - lead lead frame chip scale package [lfcsp_wq] cp - 48 - 13 adp5053 - eva lz evaluation board 1 z = rohs compliant part. 2 table 16 lists the factory default options for the device. to order a device with options not listed, contact your local analog devices sales or distribution representative. ? 2013 C 201 6 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d 11636 -0- 10/1 6(b)

▲Up To Search▲

Price & Availability of ADP5053ACPZ-R7

	To Download ADP5053ACPZ-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .